by Zhebo Chen

Dec 22, 2020

In my previous blog, I described how Applied Materials’ novel selective deposition process removes a critical bottleneck to continued 2D scaling in foundry-logic nodes. This breakthrough in materials engineering is part of a portfolio of selective processing technologies that Applied has been building over the past two decades. In this blog, I will explain what selective processing is and how it enables chip scaling to continue delivering improvements in power, performance, area/cost and time-to-market (PPACt).

Selective vs. Traditional Processing

Traditional wafer processing methods involve steps that uniformly affect all the surfaces across a wafer, without consideration for any differences in individual material properties. Historically, the industry has relied on lithography to define individual patterns that guide these processing methods into forming the transistors and the connections between them. As chips become more complex, this approach is running out of steam. Traditional processing methods are being hampered by shrinking design rules in 2D features, as well as from an inability to address architectural challenges such as smaller feature sizes, higher aspect ratios, tighter vias and edge placement errors presented by the increased use of 3D chip designs.

In contrast to traditional wafer processing methods, selective technologies use the distinctive properties of individual surfaces to tailor a process with targeted effect to a particular material of interest. It achieves this through the design of unique chemical and physical processes which recognize specific materials or features on the wafer surface. These “smart” approaches unlock a new paradigm in wafer processing that allows specific materials to be deposited only in certain areas, or to be removed or modified without impacting nearby structures.

Selective Processing Solves PPACt Challenges at Advanced Nodes

To address the scaling challenges of advanced nodes, selective processing has evolved to the point where it can be used to deposit and etch materials at the atomic scale. Think of it as a highly advanced approach to additive/subtractive manufacturing whereby individual atoms are placed and removed with incredible exactness.  As my colleague and Applied Fellow Ellie Yieh once remarked, “It’s like controlling where each snowflake should land during a blizzard.”

For example, with selective processing, the chemistry in a chemical vapor deposition (CVD) process can be tuned to interact and deposit only on a metallic surface, leaving any non-metallic surfaces free of deposited material. This is the technology employed in Applied’s selective tungsten process which allows chipmakers to eliminate space-consuming liners and nucleation layers traditionally used to enable tungsten to be filled in transistor contact vias (see Figure 1).