by Zhebo Chen

Jul 16, 2020

In my previous blog, I described how increasing contact resistance is becoming a major bottleneck to transistor power and performance.

Now I will explain why contact resistance has become more challenging to the foundry-logic roadmap, reaching a point where an entirely new approach to building transistor contacts is needed to scale to the 5nm node and beyond.

Previously, I explained how the cladding layers in tungsten (W) transistor contacts are becoming a major cause of contact resistance. The cladding is in the form of a titanium nitride (TiN) liner-barrier and a W nucleation layer. These layers serve a critical function of ensuring that the contact adheres well to surfaces and grows evenly, without defects—but they do a very poor job of conducting electrons.

To make an analogy, think about painting a wooden fence: you apply a coat of primer before applying a thin, first coat of paint and then a thick, final coat. Similarly, without the TiN barrier, the bulk W adheres poorly to the surfaces and simply flakes off. Without the W nucleation layer, the bulk W doesn’t grow.

Unfortunately, these “preparation layers” have become increasingly problematic because they do not scale. The result is that a higher percentage of the available volume goes to the liner-barrier while a dwindling percent goes to the W conductor. With each foundry-logic node, contact resistance increases, starving the finely engineered transistor and chip and preventing them from achieving their power and performance potential.

Another challenge to the traditional W fill process is that a seam forms, further increasing resistance and potentially impacting yield in high-volume production (see Figure 1).