by Nirmalya Maity, Ph.D.

Sep 02, 2021

As a follow-on to my colleague Mike Chudzik’s recent blog, I will preview the second topic to be featured at our Master Class event next week: heterogeneous design and advanced packaging.

For decades, PPAC was enabled by 2D shrinking and monolithic semiconductor integration which delivered simultaneous improvements in chip performance, power and area/cost—just like clockwork. But as classic Moore’s Law 2D scaling slows and becomes more expensive, chipmakers are increasingly moving in the direction of heterogeneous design and on-package integration of chiplets and devices to accelerate PPAC and time to market (PPACt™). Let’s examine the evolving design trends that are enabling this shift and see where the packaging roadmap is headed.

The Rise of Heterogeneous Design

Historically, the primary function of semiconductor packaging was to protect the die and connect it to a printed circuit board (PCB). It was often regarded as a low-value, commodity part of the industry. Also, PCBs served the critical role of routing power and signals between chips and modules. But as computing has progressed from PCs to mobile devices and now the AI era, designers are rethinking how to best integrate both chips and systems. Heterogeneous design and advanced packaging are now a competitive imperative for the world’s leading semiconductor and systems companies.

Fueling this evolution is the paradox that data is growing exponentially while classic Moore’s Law scaling is slowing. We can no longer count on exponential increases in transistor density and speed and like reductions in area/cost. As a result, designers are finding it harder to place all of the transistors they need for high-performance computing, machine learning and inferencing on a single die. As an alternative approach, system designers are seeing the potential to use multi-die advanced packages instead of individually packaged die on a PCB, enabling high-performance logic and memory to be put in closer proximity to reduce latency and power consumption. In short: today, packaging is about more than protection – it’s about PPACt.

Enabling the “PPA” in PPACt …

Compared to the legacy chip on PCB approach, advanced packaging enables substantial increases in I/O density and reductions in latency and power. Using today’s through-silicon vias (TSVs) rather than bump-to-PCB connections, designers can already increase I/O density by approximately 100X and reduce energy per bit transfer by approximately 15X depending on architecture and workload. The next revolution in advanced packaging is hybrid bonding whereby chips and wafers can be directly connected in copper with no need for an interposer. Compared to TSVs, hybrid bonding will enable another 10X increase in I/O density and another 2X improvement in energy per bit.

... and the “Ct” in PPACt

Heterogeneous design can also reduce cost and speed time to market. Monolithic approaches can result in very large die that are expensive to design, debug and tape out. Heterogeneous approaches allow engineers to disaggregate a design into smaller chiplets that can be connected in a single, high-performance package. Smaller die typically have higher yields and lower costs. Also, leading-edge-node wafers are typically more expensive than wafers based on previous nodes, so engineers can mix and match performance-critical die with other chiplets, resulting in a lower blended cost. In addition, proven IP chiplets can be incorporated more quickly. This mix-and-match flexibility can speed time to market.