by Amulya Athayde and Ramesh Chidambaram
May 20, 2024

Nvidia’s CEO Jensen Huang famously referred to the launch of OpenAI’s ChatGPT as an “iPhone moment” for artificial intelligence, describing it as “one of the greatest things that has ever been done for computing.”^[1] The Large Language Models powering today’s most advanced AI chatbots are estimated to have more than a trillion parameters – features that can be adjusted to optimize system performance – with future models expected to use an order of magnitude more. A massive amount of high-bandwidth memory (HBM) is required to support such large models and enable more energy-efficient AI training and inferencing. In fact, Huang has described HBM as a “technology miracle.”^[2]

The need for HBM in high-performance AI has implications for the wafer fab equipment market. HBM made up only a modest amount of DRAM output in 2023 but is expected to grow at a 50-percent compound annual growth rate over the coming years. This is helping to drive healthy demand for DRAM wafer processing equipment and the associated capabilities needed to create HBM stacks. Applied Materials is the leading process equipment player in this space, with a broad range of enabling technologies for both leading-edge DRAM and 3D packaging.

A Legacy of Leadership

The primary components underpinning HBM are leading-edge DRAM chips. Today’s HBM stacks contain up to eight DRAM dies, with chipmakers planning to increase to 12 and beyond in the near future. At Applied, we have made strategic investments over the past decade to build and solidify our position as the industry’s leading provider of DRAM processing equipment. In 2023, our DRAM share was more than 10 points higher than it was a decade earlier, and our DRAM revenues were larger than our two closest process equipment peers combined. Our share of HBM packaging process equipment spending currently exceeds 50 percent.

We have deployed several innovations developed for logic to DRAM, to enable better density scaling and deliver significantly improved performance and power-efficiency. For example, memory manufacturers have recently followed logic chipmakers in adopting our high-k metal gate (HKMG) transistor technologies, which use exotic materials to improve gate capacitance and reduce leakage. This materials inflection in DRAM is being enabled by multiple Applied deposition technologies that help form the complex and delicate HKMG materials stack and fine-tune transistor performance. We have deployed similar innovations across other DRAM processing steps, including a new low-k dielectric material to overcome interconnect resistance challenges and a co-optimized CVD hard mask material and etch system to accelerate capacitor scaling.

While innovation in DRAM chips is important, the density and bandwidth behind HBM is realized through advanced 3D packaging. The HBM manufacturing flow adds around 19 materials engineering steps to the approximately 700 process steps needed to make a conventional DRAM – and Applied serves about 75 percent of these steps with our equipment.

A critical ingredient in HBM DRAMs is through-silicon vias (TSVs) – vertical wires used to electrically connect the stacked chips. Applied was an early pioneer in TSV development. Nearly 15 years ago, Applied became a key collaboration partner with the European research organization imec to formulate the industry’s first TSV process flow and integration scheme. The collaboration led to the creation of the TSV standards used in HBM today.

Since that milestone, Applied has developed several additional, unique solutions for TSVs and other HBM packaging steps. These technologies take full advantage of our deep capabilities in chip interconnect wiring, leveraging several front-end wafer processing equipment technologies to enhance the back-end packaging steps needed to build HBM stacks. Our strength as the industry’s #1 provider of processing equipment for advanced packaging has helped us build our leadership position in HBM. In fact, we expect our HBM packaging revenues to grow by as much as 6X in fiscal 2024, growing to more than $600 million.

A Broad Packaging Portfolio

As highlighted earlier, HBMs require around 19 incremental materials engineering steps. On the front side of the wafer, 10 HBM steps are needed to create frontside interconnect pillars and TSVs, which are formed by etching trenches into silicon and then filling them with insulating liners and metal wires. After the frontside wafer processing is completed, the wafer is flipped for backside processing, with a further nine materials engineering steps needed to reveal the TSVs and create backside interconnect pillars.