In the channel and shallow trench isolation module, the industry has been increasing fin height and reducing fin width over several technology nodes to increase speed. We are reaching a point, however, where taller, narrower fins are more susceptible to bending during the manufacturing process due to strains caused by the isolation oxide that needs to be placed between the fins. This bending causes counteractive strain which degrades electron mobility and impacts threshold voltages, resulting in increased transistor variability (see Figure 2). To counteract fin bending requires new materials engineering solutions.

Restoring Interface and HKMG Scaling Parity

The HKMG module is the heart of the transistor. These metal stacks are highly complex and can contain upwards of seven layers, including the interface, high-k and metal-gate layers (see Figure 3). Interface and high-k scaling are critical to gate-oxide reduction, which boosts transistor drive current. The metal gate is tuned to ensure the transistor has the correct work function, which determines the threshold voltage. The issue is, since the 14nm node, the interface and high-k layers haven’t scaled at the same rate as other physical parameters that make higher transistor drive current possible. New innovations are needed to restore interface and high-k scaling parity.

Contact Volume Eroded with Each New Process Node

The third major transistor element is the transistor source/drain resistance module. Each new process shrink has reduced transistor contact area by roughly 25 percent per node. The smaller area drives up resistance. The main contributors are interfacial resistance between the metal contact and silicon transistor, and external resistance within the source and drain regions (see Figure 4).

Mitigating interfacial resistance and external source/drain resistance requires new materials and the co-optimization of multiple process steps.

Laying the Groundwork for Gate-All-Around Transistors

As previously discussed, FinFET fins are becoming unsustainably tall and narrow. Controlling fin width has become harder with each new process shrink, which has led to increased variability in threshold voltages that degrades device performance. The industry is rapidly moving to enable a new architecture called gate-all-around (GAA) where the silicon channels are flipped along their side and stacked up like a layer cake (see Figure 5).

GAA transistors provide a new way to solve channel thickness variability by replacing the traditional lithography- and etch-based control method. Using epitaxy and selective removal instead enables extremely precise thickness control. From a performance perspective, the GAA architecture lowers variability while enabling gate length scaling to increase drive current by 10 to 15 percent, while simultaneously reducing power consumption. Applied Materials is enabling these and other techniques by combining new materials with technologies like selective etch and eBeam metrology, areas we are uniquely positioned to address thanks to the breadth and depth of our technology portfolio.

In the next blog in this series, my colleague Mehul Naik, will discuss challenges to reducing resistive-capacitive (RC) delay and power consumption in logic interconnects.

Tags: logic, scaling, PPACt, transistor, interconnect, Patterning, DTCO, 3nm, FinFET, gate all around, high k metal gate, HKMG