Packaging connects the chip to the rest of the system and helps protect it from physical damage and environmental threats, including moisture, humidity and radiation. The package can also help dissipate heat so that the chip can operate cooler and more reliably.

Packaging is an important lever in driving PPACt. Bringing the memory closer to the processor with advanced packaging increases bandwidth and performance and reduces power. Multi-chip packages and heterogeneous integration can reduce cost and improve performance. Instead of combining all of a chip’s functions on a single, large, silicon die, designers can mix and match die based on the most cost-effective process technology. They can electrically connect a variety of die with multi-chip packaging technologies, including interposers and redistribution layers that bring them closer together than on a traditional motherboard. These multi-chip packaging approaches can also be combined with 3D stacking using through-silicon vias (TSVs).

The need for high-performance, energy-efficient AI computation is helping accelerate packaging innovation. For such applications, designers can bring large numbers of computing cores and high-bandwidth memory close together to speed the flow of data to and from the cores. TSV and advanced packaging techniques like fan-out wafer-level packaging, which use interposers and redistribution layers, can also be used in high-performance mobile applications like advanced smartphones to combine computing and memory in the smallest form factor.