CAPACITANCE

• The degree to which a material can store an electrical charge.

CAPACITOR

• An electrical component used to temporarily store a charge. It consists of two conducting surfaces separated by a non-conducting dielectric.

CARRIER

• An electron or hole that carries electric charge through a conducting or semiconducting material.

CARRIER MOBILITY

• A measure, typically specified in cm²/V·s, of how rapidly a charge carrier (an electron or hole) can move through a semiconductor in response to an applied electric field. The conductivity of a material is proportional to mobility multiplied by the concentration of carriers. High mobility is highly desirable in semiconductor devices because it leads to higher device performance through faster transistor switching.

CASSETTE

• A metal or plastic open container used for transporting wafers (usually 25) to and from a tool. Cassettes protect wafers from damage that could be caused by direct handling.

CD-SEM (CRITICAL DIMENSION SCANNING ELECTRON MICROSCOPE)

• A type of scanning electron microscope used to measure critical dimensions.

CD-TE

• A category of thin-film solar cells that uses a cadmium-tellurium compound as the light-converting active layer.

CDU (CRITICAL DIMENSION UNIFORMITY)

• a parameter used in etch to describe precision of the etch process. CDU is defined as the variation of the size of a repeating feature from its nominal value (CD) measured at several points across the substrate.

CFD

• Computational Fluid Dynamics, a branch of fluid mechanics that uses numerical methods and algorithms to solve and analyze problems that involve fluid flows.

CHANNEL

• In a FET, the channel is the semiconducting region through which electrons flow between the source and drain terminals, as controlled by a voltage applied to the gate.

CHANNELING

• In ion implantation, channeling occurs when some ions in a beam strike the wafer between atomic lattice structures of single-crystal silicon and penetrate deeper than the other ions. Channeling is undesirable since the depth of the implant cannot be accurately calculated or controlled. Channeling can be reduced by tilting or rotating the wafer, covering its surface with a screen oxide, or pre-amorphizing the silicon.

CHARGE EXCHANGE

• The loss of an electron by an atomic particle to an ionized atom.

CHIPLET

• A small integrated circuit that performs a specific function; multiple chiplets are integrated during advanced packaging.

CIS (CIGS)

• Copper Indium Diselenide: a type of thin film solar cell material that uses a compound of copper, indium, selenium. A fourth element, gallium, may also be added to the compound (CIGS) to achieve higher efficiency.

CLEANROOM

• An area in a fab where the air is conditioned to remove airborne particles that could prevent the correct function of semiconductor devices.

CMOS (COMPLEMENTARY METAL OXIDE SEMICONDUCTOR)

• A MOS device consisting of paired p-channel and n-channel transistors.
• Also used to refer to the family of manufacturing processes used to construct integrated circuits that feature CMOS transistors.

CMP (CHEMICAL MECHANICAL PLANARIZATION)

• A process that uses an abrasive, chemically active slurry to physically abrade the microscopic topographic features on a partly processed wafer so that subsequent processes can begin from a flat surface. Also referred to as chemical mechanical polishing.

CO-IMPLANTATION

• An ion implantation technique that implants two species into the same region of the material in order to improve the electrical properties of the doped region, typically to improve transistor performance.
• For example, non-dopant atoms, such as fluorine or nitrogen may be co-implanted with dopants such as boron to produce ultra-shallow PMOS transistor channels with improved dopant activation and a very sharp transition from the doped to the undoped regions.

CO-PLANARITY

• The bottom surface of the package is parallel to the landing surface of the printed circuit board.

COLD FIELD EMISSION (CFE)

• eBeam technology, where electrons are emitted from a source at low temperatures to image a sample with higher resolution and speed than TFE.

COLOR FILTER

• A layer of an LCD flat panel display that is divided into transparent areas of red, green and blue, each of which overlays a transistor which is switched on an off to the full range of colors.

COMPLEMENTARY FET (CFET)

• An attractive transistor architecture for beyond 1nm logic nodes, where NMOS and PMOS devices are stacked on top of one another to reduce cell footprint compared to gate-all-around transistors.

COMPUTER AIDED DESIGN (CAD)

• The use of computer systems and software to aid creation, modification, or analysis of 2D or 3D designs.

COMPUTER INTEGRATED MANUFACTURING (CIM)

• A manufacturing approach using computers to control the entire production process, allowing individual steps to exchange information and initiate actions.

CONDUCTOR

• A material that contains mobile charge carriers, such as electrons or ions.

CONTACT

• A feature on a chip that forms the electrical pathway between the first interconnect layer and the transistor. This area is often filled with tungsten.

CONTINUOUS WAVE

• In RF plasma generation, refers to a waveform that is maintains a constant frequency and amplitude, as opposed to "pulsed" delivery where the supply is modulated, typically between two different amplitudes, at a frequency in the 100-1000Hz range.

COPPER INTERCONNECT

• An interconnect structure using copper as the conducting material, providing improved device speed and lower power consumption compared with aluminum interconnects.

COPPER SEED LAYER

• A thin copper layer, usually deposited by physical vapor deposition, which acts as a wetting and nucleation layer for successful subsequent copper bulk film deposition by electrochemical plating.

CPD (CONFORMAL PLASMA DOPING)

• A doping process that deposits a conformal layer of material containing the desired dopant species and then uses a thermal process to drive the dopants to a controlled depth in the underlying circuit structures. CPD provides a means to dope complex, 3D structures. Doping is traditionally performed by ion implantation, which bombards the wafer with dopant ions moving at high speed. However, this line-of-sight bombardment process cannot provide uniform doping of 3D structures. More importantly, the fast-moving ions can damage the ultra-thin semiconductor layers in cutting-edge chips. CPD is designed to solve both problems.

CRITICAL DIMENSION (CD)

• In photolithography, CD is the minimum features size that is to be patterned on the wafer. In other semiconductor processes, CD is the size of a feature found at several points across the substrate used to describe the accuracy or other characteristic of a given process.

CROSSTALK

• An undesirable effect whereby a signal in a circuit element, such as an interconnect line, affects the signal in another nearby circuit. In semiconductors, the coupling is usually a result of parasitic capacitance between the two circuits.

CRYOGENIC COOLING

• Reducing the temperature of a material to -100°C or lower.

CRYOGENIC IMPLANTATION

• A technique used in damage engineering where the substrate is cooled to temperatures as low as -100°C.
• Ion implantation into cooled substrates improves of amorphization properties and can reduce the formation end-of-range defects, leading to reduced leakage currents.

CRYOPUMP

• A type of secondary vacuum pump that captures gas molecules by cryogenically freezing and absorbing them. Cryopumps are capable of creating a very high vacuum but must periodically be regenerated, i.e., allowed to return to ambient temperature to desorb and pump away the captured gas species.

CRYSTALLINE

• A material that has atoms arranged in an ordered periodic array.

CRYSTALLINE SILICON (c-Si)

• A generic term for solar cell technology that uses a substrate of purified silicon in a crystalline structure.

CVD (CHEMICAL VAPOR DEPOSITION)

• A process for depositing thin films by exposing the substrate to one or more volatile precursors, which react and/or decompose on the substrate surface.

CYCLE TIME

• The amount of time required for a wafer to process through a particular part of the manufacturing process.

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DAMAGE ENGINEERING

• A class of techniques using in ion implantation used to control the electrical characteristics of a semiconductor device by intentionally disrupting the silicon crystal structure.
• In particular, damage engineering is used to control the depth to which dopants are diffused by adjusting ion dose rate, employing cryogenic implantation, and/or using co-implant species.
• In fabricating transistor with very small geometries, damage engineering is used to enable performance-enhancing techniques such source-drain extensions, pre-silicide and strain engineering.

DAMASCENE

• A means of creating copper metal interconnects by over-filling trenches in the interlayer dielectric using ECD then using CMP to remove the excess copper.

DARC (DIELECTRIC ANTI-REFLECTIVE COATING)

• A non-reflective, non-energy-absorbing, inorganic dielectric layer deposited on top of metal or polysilicon to improve lithography performance.

DARKFIELD INSPECTION

• A defect inspection technique that uses detectors that collect scattered light to make a defect appear bright against a dark background. Typically used to find particles on wafers during interconnect fabrication. Compare with brightfield inspection.

DEEP ULTRAVIOLET (DUV)

• The portion of the ultraviolet light spectrum with wavelengths below 300nm.

DEFECT

• Any foreign substance on the wafer (physical defect) or parts of a pattern that are missing or do not belong (pattern defect).

DEFECT INSPECTION

• A process where defects are located on a patterned wafer. A list of defect locations is created and passed to a DR-SEM for review and classification.

DEFECT REVIEW SCANNING ELECTRON MICROSCOPE (DR-SEM)

• A type of scanning electron microscope used to classify defect types during the wafer manufacturing process and determine whether these defects will affect chip yields.

DEGASSING

• The removal of dissolved gases from liquids.

DEPOSITION

• A process used to deposit a thin layer of insulating or conductive material onto the substrate.

DESIGN RULES

• Rules that outline geometry and connectivity restrictions for the design and layout of integrated circuits.

DIE

• In semiconductor manufacturing, the area of the silicon wafer on which a functional circuit is fabricated. Many hundreds of identical dies (alternative plurals are die and dice) are fabricated on each wafer.

DIELECTRIC

• An insulator.
• Also used more specifically to refer to an insulator that may be polarized by an applied electric field. Two dielectrics commonly used in semiconductor processing are silicon dioxide (SiO₂) and silicon nitride (Si₃N₄).

DISK

• The large conical wheel on a batch processing ion implanter used for holding wafers during ion implantation. A wafer is mounted at the end of each "spoke" of the disk. As the disks spins, each wafer in turn passes through the ion beam which is scanned radially to deliver a uniform dose across each wafer.

DOPANT

• An impurity added in controlled amounts to a material in order to modify some intrinsic characteristic, such as resistivity or melting point. The addition of a dopant to a semiconductor creates a material with predominantly negative (n-type) or positive (p-type) charge carriers depending on the dopant species.

DOPANT PASTE

• A viscous liquid or suspension containing dopant material.

DOPING

• The introduction of impurities, or dopants. into the crystal lattice of a material to modify its electrical properties. To create n-type regions, arsenic (As), arsine (AsH₃), phosphine (PH₃) and antimony (Sb) are commonly used. For p-type regions, typical dopants are boron (B), Boron Difluoride (BF₂) and Boron Trifluoride (BF₃).

DOSE

• The total amount of dopants measured in ions/cm² needed to give the implanted wafer the desired electrical properties.

DOSE PROCESSOR

• A precision current measuring device used to calculate the total number of ions implanted into a wafer. The function is sometimes combined with uniformity monitoring.

DOUBLE PATTERNING

• A class of patterning techniques designed to double the density of circuit features that can be produced on the wafer at the resolution limit of a particular lithography stepper.

DOUBLE PRINT

• A technique used in solar PV manufacturing where contact lines or other structures are built up in multiple, precisely-aligned screen printing operations.
• Example applications of double print include the fabrication of narrower, taller contact lines and selective emitter cell types.

DPN (DECOUPLED PLASMA NITRIDATION)

• A method that uses inductive coupling to generate nitrogen plasma and incorporate nitrogen into the top surface layer of an ultra-thin gate oxide to increase the dielectric constant of the gate dielectric.

DPS (DECOUPLED PLASMA SOURCE)

• A type of ICP plasma source used primarily for etch applications that separates the management of plasma density and ion energy, resulting in high etch rate and minimal plasma damage to the substrate.

DRAIN

• The output terminal of a FET.

DRAM

• A type of volatile computer memory where each bit is stored in a separate capacitor. Because capacitors self-discharge over time, the state of each bit must be refreshed approximately 15 times per second, hence the term "dynamic". Compare with "static" flash memory.
• DRAM offers the fastest programming of any type of memory, making it highly suitable for direct connection to a microprocessor for use as main memory.

DUAL DAMASCENE

• A Damascene process designed to form and fill two features with copper at once, e.g., a trench overlying a via may both be filled with a single copper deposition step.

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eBEAM (ELECTRON BEAM)

• An imaging technology, where primary electrons are fired at a sample in order to gather information such as secondary electrons or backscattered electrons and produce an image.

ECA (ELECTRICALLY CONDUCTIVE ADHESIVE)

• Composite material comprising a resin component enabling adhesion and conductive particles suspended into it enabling conductivity. When the resin component is cured, the conductive particles get in contact to each other enabling the electrical conductivity.

EDGE PLACEMENT ERROR

• The difference between the intended and the printed features of an IC layout. In metrology, it is a metric based on extreme value statistics that combines all the variations both in CD and Overlay domains.

EFFICIENCY

• In solar PV technology, the fraction of incident solar energy that is converted to electrical energy.

ELECTRO-MIGRATION

• Movement of material caused by ion motion in a conductor that arises from the momentum transfer between conducting electrons and diffusing metal atoms.

ELECTROCHEMICAL DEPOSITION (ECD)

• A deposition process in which metals are removed from a chemical solution and deposited on a charged surface. Also referred to as electrochemical plating, electroplating, or electrodeposition.

ELECTRODE

• An electrical conductor used to contact a nonmetallic part of a circuit (e.g., a semiconductor).

ELECTROLYTIC

• Performed by means of electrolysis, which is the process of separating a liquid into its different chemical parts by passing an electric current through it.

ELECTROMAGNETIC INTERFERENCE (EMI)

• The effect resulting from multiple sources emitting electromagnetic waves at the same frequency spectrum.

ELECTRON

• A stable subatomic particle with a negative electric charge that acts as a carrier of electricity.

ELECTRON FLOOD

• In ion implantation, a source of electrons in the end station in the vicinity of the wafer, used to neutralize undesirable charge buildup from the positively-charged implant ions that could damage sensitive circuit features.

ELECTRON VOLTS (eV)

• The energy gained by an electron (or proton, same size of electric charge) moving through a voltage difference of one volt. In ion implantation, eV is used as a measure of the momentum of a particle. A particle with a higher momentum will penetrate further into the semiconductor lattice than one with less momentum.

ELECTROSTATIC

• A static voltage field in which no current is flowing. In ion implantation, it refers to using voltage to bend or focus an ion beam.

ELECTROSTATIC CHUCK (ESC)

• A metal base-plate maintained at a high voltage relative to the wafer that rests upon it, so that an electrostatic force clamps the wafer to it.

ELECTROSTATIC MIRROR

• A negatively charged electrode that reflects electrons - a beam filter.

EMITTER WRAP-THROUGH (EWT)

• A type of advanced back contact PV cell. In the Emitter Wrap Through cell structure, a continuous emitter is diffused through thousands of laser drilled vias less than 100 µm (micrometer) in diameter taking current to the back of the cell. By eliminating the front contacts, EWT enhances light absorption and increases cell efficiency.

END STATION

• The area of an ion implanter where wafers are handled and processed.

END-OF-RANGE DEFECT (EOR)

• Also, known as end-of-range dislocation loops, EOR defects are imperfections in the silicon crystal lattice found immediately below the interface between the amorphized and crystalline regions of the transistor channel after ion implantation.
• EOR defects can be minimized using cryogenic implantation.

ENERGY PURITY MODULE (EPM)

• A beamline element used in certain Varian ion implanters that simultaneously decelerates the ion beam to the final energy and filters the ion beam to remove unwanted high-energy components that can “smear” the transistor channel, leading to increased leakage current and decreased performance.

EOT (EQUIVALENT OXIDE THICKNESS)

• A number used to compare performance of gate dielectric materials by indicating how thick a silicon oxide film would need to be to produce the same effect as the dielectric material being used.
• A number used to compare performance of high-k dielectric MOS gates with performance of SiO₂-based MOS gates. It shows thickness of SiO₂ gate oxide needed to obtain the same gate capacitance as one with thicker SiO₂ dielectric with higher dielectric constant k [e.g., EOT of 1-nm would result from using a 10 nm thick dielectric featuring k=39 (k of SiO₂ is 3.9)].

EPITAXY (Epi)

• A method of depositing, or growing, a monocrystalline film where the deposited film takes on a lattice structure and orientation identical to those of the substrate. This enables a high-purity starting point for building a semiconductor device.

EPT (EQUIPMENT PERFORMANCE TRACKING)

• An APC technique that monitors processing tools to provides visual and statistical reporting tools to identify bottlenecks and improve factory performance.

ETCH

• A process for removing material in a specified area through a chemical reaction or physical bombardment. The process can be performed using liquid-phase (wet) etchants or under vacuum (dry) typically using a plasma to generate gas-phase reactants.

ETCHANT

• Substances, including acid or corrosive chemicals, used to etch wafers.

ETCH RATE

• The rate at which material is removed during etch processing, typically expressed in Å/s or nm/s.

ETCH STOP LAYER (ESL)

• A film layer used to restrict etch depth and protect underlying material. The ESL is chosen to be resistant to the etch chemistry being used.

EUVL (EXTREME ULTRAVIOLET LITHOGRAPHY)

• A lithography technique using 13.5nm EUV illumination. It represents a significant departure from DUV lithography because all the optical elements must act in a reflective mode and the entire optical system must be kept under vacuum.

EXCURSION

• A deviation from parameters specified for a process.

EXTRACTION ELECTRODE

• In ion implantation, the extraction electrode is used for extracting positively charged ions from the source. Ions exiting the source combine downstream to form a beam which is used to implant dopants into a silicon wafer.

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FAB

• Common name for a semiconductor fabrication plant, a factory used to manufacture integrated circuits.

FAN-OUT

• Also known as Embedded Wafer-Level Ball Grid Array. A chip packaging scheme in which the package is not created on a silicon wafer, but on an artificial wafer made of molding material (e.g., epoxy). The distance between chips is typically larger than on a silicon wafer. Interconnects are created around the chips and electrical connections are made from the chip pads to the interconnects. Any number of additional interconnects can be created on the package in an arbitrary distance (fan-out design), making this scheme ideal for space-sensitive applications in which the chip area would be insufficient to place the required number of interconnects at a suitable distance.

FDC (FAULT DETECTION AND CLASSIFICATION)

• An APC technique that uses process state models to deduce the occurrence and location of a fault condition and diagnose the cause of the fault.

FEOL (FRONT-END OF LINE)

• The first portion of integrated circuit fabrication including transistor fabrication. FEOL generally covers everything up to (but not including) the deposition of contacts and metal interconnect layers. The term front end is sometimes used to refer the entire process to completed wafers.

FET (FIELD EFFECT TRANSISTOR)

• A type of transistor that relies on an electric field to control the flow of charge carriers in a semiconductor material.

FI (FACTORY INTERFACE)

• An ultra-clean enclosure mounted to the front of a semiconductor processing system that transfers wafers to and from the cleanroom environment and the interior of the system.

FIELD

• A term used in deposition applications to describe the top surface of a wafer as distinct from the surfaces of circuit features such as trenches and vias that are lower than the top surface.

FINFET

• A FinFET is a type of FET in which the conducting channel is surrounded on three sides by a thin silicon "fin" which forms the gate of the transistor. Although technically the term only refers to a design with two gates, the term is often used to describe any multi-gate transistor architecture, regardless of the number of gates.
• The main design goal of the FinFET is to reduce current leakage while the transistor is in the "off" state.

FLASH MEMORY

• A type of non-volatile storage technology that requires no power to retain data, unlike DRAM. The name "flash" comes from the fact that the memory is erased and programmed in large blocks, from hundreds to thousands of bits at a time. This inability to address individual bits makes it too slow for direct connection to a microprocessor, but the mechanical robustness and low cost of flash makes it ideal for mass storage in mobile devices.

FLAT PANEL DISPLAY (FPD)

• Any consumer display device, such as an LCD or AMOLED, with a planar surface, in contrast to the curved front of cathode ray tube displays.

FLIP CHIP

• A method for interconnecting semiconductor devices, such as IC chips and microelectromechanical systems (MEMS), to external circuitry with solder bumps that have been deposited onto the chip pads.

FLUX

• The flow of a physical property in space, frequently also with time variation.

FOUNDRY

• A company with fabrication plants or "fabs" that produce semiconductor chips for other companies.

FORWARD VOLTAGE

• In LED technology, the voltage across the terminals of the LED that is required in order for the produce a specified light output. It is also the voltage below which the LED will not produce any light.

FRONT OPENING UNIFIED POD (FOUP)

• A container with a stationary cassette with a front opening interface used with an automated materials handling system (AMHS). The use of FOUPs can reduce particle counts on wafers because the interior of the FOUP is isolated from the ambient fab environment.

FSG (FLUORINE-DOPED SILICATE GLASS)

• An amorphous insulating material (k=approximately 3.5) made by doping SiO₂ with fluorine often used in between copper interconnect layers. Also called fluorosilicate glass.

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GATE

• A terminal of a FET that controls the flow of current between the source and drain terminals.

GATE ALL AROUND (GAA)

• A transistor in which the gate electrode is present on all four sides of the channel.

GATE STACK

• Collective term for the conductive and insulating layers that comprise the gate structure in a MOSFET.

GEN (GENERATION)

• A term, short for generation, used in FPD manufacturing to describe the size of the glass substrate.
• Each generation is approximately 80% larger than its predecessor.

GOWNING

• A procedure that includes hand washing and the donning of gloves, head coverings, masks, shoe coverings, and other specialized garments before workers enter a cleanroom.

GRAY AREA

• A support area or service area immediately outside a cleanroom that allows service personnel to perform routine maintenance without entering the cleanroom itself.

GRAYFIELD/GREYFIELD INSPECTION

• A defect inspection technique that uses detectors collecting collect mid- and high-angle scattered light to make a defect appear bright against a dark background. Typically used to find small pattern defects beyond optical resolution. Compare with brightfield inspection.

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HARD MASK

• A mask that is more resistant than photoresist to etching, used when higher etch selectivity is required than can be achieved using photoresist.

HDP (HIGH DENSITY PLASMA)

• A plasma featuring high concentration of free electrons, and hence, high concentration of ions.

HDP-CVD (HIGH DENSITY PLASMA CHEMICAL VAPOR DEPOSITION)

• A type of plasma-enhanced CVD performed under high vacuum and at high plasma excitation voltage in order to improve the ability to fill small high aspect ratio structures.

HIGH ENERGY IMPLANTER

• A class of ion implanter which can produce ion energies in excess of 1MeV, enabling dopants to be implanted well below the surface of the wafer.

HIGH-BRIGHTNESS LED (HB-LED)

• A class of LED that produces enough light to be used for illumination applications. Applications include backlighting for LCD displays, room illumination and automotive exterior lights. Exactly how bright an LED must be to qualify as "high-brightness" is not well defined. The simplest definition is one that is too bright to look at directly.

HIGH-CURRENT IMPLANTER

• A class of ion implanter which produces the highest beam currents, typically in excess of 3mA. The greater the beam current, the faster the required dose is reached, leading to higher wafer throughput. Ion energies between 1keV and 100keV are typical.

HIGH-NUMERICAL APERTURE (HIGH-NA) EUV

• A lithography technique that uses larger optics to increase numerical aperture and improve resolution. It aims to replace EUV double-patterning with a single lithography pass.

HMI (HUMAN MACHINE INTERFACE)

• User interface or dashboard that connects a person to a machine, system or device, most commonly used in the context of an industrial process to visually display data, track production time, trends and tags, monitor machine inputs and outputs and loads more.

HOLE

• In semiconductors, a hole is the absence of an electron where one could exist in a crystal lattice. It can be thought of as the opposite of an electron, with a positive charge of exactly the same magnitude as an electron. If, in an electric field, an electron moves into this vacant site, the hole has effectively moved in the opposite direction.

HOST

• The intelligent factory system that communicates with the equipment used in semiconductor manufacture. In semiconductors, the SECS/GEM protocol is used.

HOTSPOT

• An area known to be prone to failure.

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ICP (INDUCTIVELY COUPLED PLASMA)

• A type of plasma source in which the energy is supplied by electrical currents which are produced by electromagnetic induction, that is, by time-varying magnetic fields generally applied from outside the vacuum enclosure.

IGZO (INDIUM GALLIUM ZINC OXIDE)

• A semiconducting material used to form the channel of high-performance thin-film transistors for the active layer of LCDs. Compared to amorphous silicon, the conventional channel material, the higher electron mobility of IGZO allows the transistors to switch more rapidly, enabling higher-resolution displays with a faster refresh rate.

IMMERSION LITHOGRAPHY

• A lithography resolution enhancement technique that replaces the usual air gap between the final lens and the wafer surface with a liquid medium such as water.

IMPLANT

• An abbreviation for ion implantation.

IMPLANT ANGLE

• In ion implantation, the incident angle between the ion beam and the wafer surface.

INSPECTION

• The examination of a wafer to detect defects of various types (e.g., scratches, particles, damaged features) following each step in the semiconductor fabrication process flow.

INSULATOR

• Nonconductive materials used to isolate electrically active areas of the device or chip from one another. Some commonly used insulators are silicon dioxide, silicon nitride, BPSG, and PSG.

INTEGRATED CIRCUIT (IC)

• An electronic device that consists of many elements fabricated together on a single silicon substrate.

INTERCONNECT

• The wiring in an integrated circuit that connects the transistors to one another and to external connections.

INTERLAYER DIELECTRIC (ILD)

• Films used between metal layers of an IC for insulation.

INTERMETAL DIELECTRIC (IMD)

• Insulating films used between adjacent metal lines.

INTERPOSER

• A layer of silicon or some other suitable material that acts as an electrical interface routing between one socket or connection to another to spread a connection to a wider pitch or to reroute a connection to a different connection.

INVERTER

• A device to convert DC power from solar panels, for example, to AC power compatible with grid electricity.

ION

• An electrically charged atom or group of atoms formed by the loss or gain of one or more electrons.

ION IMPLANTATION

• A process technology in which ions of dopant chemicals (boron, arsenic, etc.) are accelerated in intense electrical fields to penetrate the surface of a wafer, thus changing the electrical characteristics of the material.

ION IMPLANTER

• A tool designed to inject selected dopant atoms uniformly across a substrate to a prescribed depth at a desired concentration. The technique is referred to as ion implantation.

ION SOURCE

• In ion implantation, an assembly that expels positive ions from a discharge by a negatively biased extraction electrode. The resulting ions can then be accelerated in a beamline towards a target wafer.

IONIZATION

• The process of adding to or removing one of more electrons from an electrically neutral atom or molecule. Once a particle is ionized, it can be accelerated, steered and otherwise manipulated using magnetic or electrostatic fields, as in a beamline.

ITO (INDIUM TIN OXIDE)

• A common TCO material.

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JUNCTION

• The interface between two semiconductor regions of differing dopant types. Usually refers to a p-n junction, at which the conductivity type changes from p-type to n-type.

JUNCTION BOX

• In solar modules, an environmental enclosure designed to provide a connection point for the output of the module.

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k-VALUE

• Also known as dielectric constant, often denoted by the Greek letter kappa (κ). An expression of the extent to which a material concentrates electric flux.
• In electronics, it refers to the capacitance of a material relative to silicon dioxide.
• A high k-value allows a transistor gate to be made smaller without increasing undesirable leakage.
• A low k-value is desirable in an insulating material such as one used to separate interconnects because it reduces charge build-up which wastes energy as heat, reducing the overall power consumption of a device. In addition, a low k-value allows faster signal propagation and thus faster switching speeds.

KERF LOSS

• The amount of material loss during a cutting process. In silicon wafer production, kerf loss refers to the amount of silicon consumed as part of the wafering process and plays a vital role in determining the cost, edge quality, and surface finish of a wafer.

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LABILE

• In chemistry, a term applied to something constantly undergoing or likely to undergo change. For example, if a molecule exists in a particular conformation for a short lifetime, before adopting a lower energy conformation, the former molecular structure is said to have 'high lability.' In semiconductors, it can refer to an ALD precursor chemical that reacts readily with the materials on the surface of the wafer.

LANDING ENERGY

• The amount of energy used to concentrate an electron beam on the target area and produce images in electron microscopy. Higher landing energy results in higher resolution, but higher shrinkage and pattern distortion.

LASER SCRIBE

• A technique that uses lasers to ablate the surface of a thin film PV cell in order to define interconnect patterns.

LATTICE

• The orderly arrangement of atoms in a crystalline solid.

LEADING EDGE LOGIC

• Current three most advanced nodes in logic, synonymous with advanced logic.

LEAKAGE CURRENT

• Wasted energy that impacts energy efficiency and signal quality.

LED (LIGHT-EMITTING DIODE)

• A semiconductor device that emits light when an electric current flows through it. An LED consists of a p-n junction which is constructed in such a way that a photon of light is emitted when a pair of charge carriers recombine.

LINEARITY

• A parameter chiefly used in photomask etch that measures the precision of the etch process. Linearity is defined as the range of deviation from target CD across a specified range of features sizes.

LINEWIDTH

• The width of a metal interconnect line.

LIQUID CRYSTAL DISPLAY (LCD)

• A type of flat panel display that uses an array of backlit thin film transistors called a backplane to control each pixel.
• An LCD works by individually controlling each transistor to allow or block the light from a backlight. The white light then passes through an array of color filters to assemble the final, full-color image.
• When a pixel transistor is turned off, the liquid crystal material rotates polarized light through 90°, allowing it to pass through the second polarizer.
• When the transistor is energized, the liquid crystal molecules align in such a way that the light is no longer rotated, so the light is blocked by the second polarizer.

LITHO ENABLING

• Any technique that enhances the resolution, fidelity or other aspect of the lithography process.

LITHOGRAPHY

• The transfer of a pattern or image from one medium to another, such as from a photomask to a wafer using a stepper.

LOAD LOCKS

• A chamber used to transfer a wafer or wafers between the atmospheric pressure of the FI and the vacuum environment used for processing.

LOGIC

• Semiconductor device that implements a basic logical operation performed on one or more digital input signals to produce a digital output signal; also, analog switches that connect or disconnect the conducting path of an analog signal.

LOT

• A batch of wafers of identical characteristics that are processed at the same time. Lots are typically kept together in FOUPs.

LOW PRESSURE CVD (LPCVD)

• A CVD process performed in an environment below atmospheric pressure.

LSI (LARGE SCALE INTEGRATION)

• A chip with between 3,000 and 100,000 transistors on a single die. The first LSI chips were produced in the mid- 1970s.

LTPS (LOW TEMPERATURE POLYSILICON)

• A process used to create polysilicon films using a two-step process. The first step deposits a precursor film at 400-450° using a PECVD process, lower than the 600-1000° LPCVD process typically used in semiconductor manufacturing. The second step uses an anneal process to convert the precursor into polysilicon.
• LTPS films are commonly used in AMOLED and ultra-high resolution TFT-LCD displays.

LUMINOUS EFFICACY

• In LED technology, a measure of how efficiently an LED converts energy to electromagnetic radiation. Usually expressed in lumens per watt (lm/W).

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MAGNETORESISTANCE (TMR)

• The property of a material (typically ferromagnetic) to change the value its electrical resistance in an externally applied magnetic field. This effect is used as a data storage mechanism in magnetic random-access memory structures.

MASK

• A patterned layer of material used to prevent the etching of the material directly beneath it. Also an abbreviation of PHOTOMASK.

MASS ANALYZER MAGNET

• The mass analyzing magnet in Varian implanters is positioned between the source and the process chamber to deflect and filter ions so only selected ions enter the process chamber. This ensures that only the required dopants reach the wafer.

MATERIAL CONTROL SYSTEM (MCS)

• A computer controlled system which manages the transporting and storing of work in progress material in a manufacturing environment.

MATERIALS ENGINEERING

• Materials engineering studies the science of the properties, structure and processes of materials. Engineering the composition of materials by creating, shaping, modifying, analyzing and even removing properties is the basis for the amazing capabilities of electronics you use every day.

MEDIUM CURRENT IMPLANTER

• A class of ion implanter designed for maximum dose uniformity. Beam currents range from 1µA to 5mA, at energies from 5-600keV. Medium current implanters usually have the ability to implant dopants at implant angles down to 30° from the wafer surface, enabling dopants to be implanted partially underneath existing structures on the wafer surface.

MEMORY

• Semiconductor device used for digital data storage, such as computer memory.

MEMS (MICROELECTROMECHANICAL SYSTEMS)

• Very small mechanical or electromechanical devices such as sensors and actuators fabricated using modified semiconductor device fabrication techniques.

MES (MANUFACTURING EXECUTION SYSTEM)

• A software control system for managing and monitoring work-in-process material in a manufacturing environment.

METAL OXIDE

• A type of TFT-LCD backplane that uses a metallic oxide, such as IGZO, to form the transistor channel.

METAL WRAP-THROUGH

• An alternative term for emitter wrap-through, a type of advanced back contact PV cell.

METALLIZATION

• The CVD or PVD deposition of a layer of high-conductivity metal used to interconnect devices on a chip. Metals typically used include aluminum, tungsten and copper, etc.

METROLOGY

• The science of measurement to ascertain dimensions, quantity, or capacity; the techniques and procedures for using sensors and measurement equipment to determine physical and electrical properties in wafer processing.

MICRO-CRYSTALLINE SILICON (µc-Si)

• A form of thin film silicon with very small (0.5-2µm) silicon crystals intermixed with amorphous silicon. It is usually deposited in a thin layer (typically 1-3µm) for tandem (stacked) thin film solar cells.

MICROLOADING

• The phenomenon by which identical features are etched at different rates depending on their density (e.g., dense, semi-dense) with respect to open area features.

MICRON

• (µm or micrometer) A unit of length; one-millionth of a meter.

MICROPROCESSOR

• An integrated circuit that contains arithmetic, logic and control circuitry in a single package.

MINI-ENVIRONMENT

• An enclosure or the environment created by an enclosure to keep wafers free of contamination such as a FOUP.

MOCVD (METAL-ORGANIC CHEMICAL VAPOR DEPOSITION)

• MOCVD is a type of epitaxy process used to deposit compound semiconductor films, especially those used in the manufacture of high-brightness LEDs and power electronics. In an MOCVD process, a chemical reaction takes place at the surface of a substrate between organic compounds that contain the required metals and other elements.

MODULE

• The solar module is the final packaged PV generator. In c-Si technologies, the module typically contains several dozen solar cells wired together.

MOL (Middle of Line)

• The MOL connects the transistor and interconnect parts of a chip using a series of contact structures.

MONOCRYSTALLINE SILICON

• See crystalline silicon.

MORE THAN MOORE (MtM)

• Diverse device technologies, such as RF devices, power management subsystems, sensors, actuators, and MEMS, that integrate analog functions into CMOS-based technologies.

MOS (METAL OXIDE SEMICONDUCTOR)

• a structure obtained by growing a layer of silicon dioxide (SiO₂) on top of a silicon substrate and then depositing a layer of metal or polycrystalline silicon (the latter is commonly used). Often used to describe a transistor fabricated in this way.

MOSFET

• A type of FET where the gate is isolated by a shallow layer of insulator. Constructed using MOS fabrication techniques.

MULTICRYSTALLINE SILICON

• In solar PV, a type of silicon wafer that is cast into ingots using grains of monocrystalline silicon. The ingots are then sliced into wafers and used in the manufacturing of microchips and photovoltaic cells.

MURA EFFECT

• A type of defect found in flat panel displays where areas of the display exhibit uneven brightness. Also known as “clouding”.

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N-TYPE

• Semiconductor material that has negatively charged conductivity (an excess of electrons).

NAND

• A logic operator used in Flash memory that produces an output signal only if at least one of its inputs has no signal, thus being “Not AND” (the inverse of an AND operator).

NANOMANUFACTURING TECHNOLOGY

• Solutions for the semiconductor, solar and display industries that are focused on dimensions smaller than 100nm.

NANOMETER (nm)

• A unit of length; one billionth of a meter.

NANOSHEET

• A two-dimensional nanostructure with thickness ranging from 1nm to 100nm.

NEUTRAL CUP

• A device used by some Varian implanters that measures the ion beam current during setup and acts as the trap for neutrals generated in the beamline.

NEUTRALS

• Particles traveling within an ion beam which have the same energy but no longer have a charge. Neutrals cannot be manipulated by external fields and will continue at a fixed velocity until colliding with the vacuum chamber walls or other particles.

NITRIDATION

• Conversion into a nitride.

NMOS or NFET

• A MOS transistor where the active carriers are electrons flowing between n-type source and drain regions in an electrostatically formed n-channel in a p-type silicon substrate.

NOISE

• The random, unwanted variation or fluctuation of voltage, current or other measurable parameters that interferes with a signal.

NOR

• A logic operator used in Flash memory that produces an output result that is the inverse of OR.

NUCLEATION LAYER

• A thin layer of film that promotes the growth of a subsequently deposited film.

NUISANCE DEFECT (NOISE)

• A suspected defect reported by a defect inspection system that can be ignored because it will have no effect on the functionality of the completed device. Suppressing nuisance, or "false alarm" defects is a critical capability of advanced defect inspection systems.

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ONO

• Oxide-nitride-oxynitride; multilayer metal-oxide semiconductor gate dielectric.

OPTICAL PROXIMITY CORRECTION (OPC)

• A lithography enhancement technique that modifies photomask circuit features to compensate for the non-ideal properties of the lithography process.

ORGANIC LIGHT EMITTING DIODE (OLED)

• A light-emitting device where photons are emitted as a result of electron-hole interactions in a thin film organic semiconductor.

ORIENT ANGLE

• In ion implantation, the azimuthal angle of the wafer's crystal lattice structure in relation to the beam. At different orient angles, different dopant penetration depths and channeling will be obtained.

ORIENTER

• A device that rotates the wafer prior to ion implantation to reduce the effects of channeling.

OVERSCAN

• In ion implantation, the practice of sweeping the ion beam past the edge of the wafer in order to achieve a uniform dose at the wafer periphery.

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P-TYPE

• Semiconductor material that has positively charged conductivity (a deficiency of electrons).

PANEL-LEVEL PACKAGING (PLP)

• An emerging, high-density packaging technique that places die on a panel rather than a wafer, which accommodates fewer die.

PARASITIC CAPACITANCE

• The inherent capacitance of all circuit elements such as interconnects and transistors which causes their behavior to deviate from “ideal” circuit elements.
• In semiconductors, refers particularly to the undesirable capacitance between closely-spaced conductors that can lead to effects such as crosstalk.
• Parasitic capacitance can be reduced by lowering the dielectric constant, or k-value of the insulator that separates adjacent circuit elements.

PARETO

• A vertical bar graph in which values are plotted in decreasing order of relative frequency from left to right. Useful for analyzing what problems need attention first.

PASSIVATION

• A layer in a semiconductor device that forms a hermetic seal over the circuit elements, either as the final step in manufacturing or to protect chemically-active materials from reaction as wafers are transferred between processing tools. Plasma nitride and silicon dioxide are the materials primarily used for passivation.

PATTERNING

• In semiconductor manufacturing, the creation of desired circuit geometry on a wafer. Generally used to refer to the combination of lithography and related processes such as patterning film deposition and etch.

PECVD (PLASMA ENHANCED CHEMICAL VAPOR DEPOSITION)

• A CVD process using plasma energy to drive the deposition. This technique allows lower deposition temperatures, increases film density and purity.

PELLICLE

• A sheet of clear polymer that rides on a frame to protect the patterned region of a photomask from airborne contamination. During exposure, any contamination is held out of the focal plane and thus does not "print" on the wafer.

PERC (PASSIVATED EMITTER REAR CONTACT)

• Modified conventional cells that can achieve higher energy conversion efficiency through the addition of a dielectric passivation layer on the rear of the cell. The dielectric passivation layer contributes to the increase of efficiency by reducing the electron recombination, increasing the solar cell’s ability to capture light and reflecting specific wavelengths that normally generate heat out of the solar cells.

PHASE SHIFT MASK (PSM)

• A photomask that take advantage of the interference generated by phase differences to improve image resolution in photolithography.

PHOSPHORUS-DOPED SILICATE GLASS (PSG)

• An amorphous insulating material made by doping SiO₂ with phosphorus to improve moisture resistance and reflow characteristics. Also called phosphosilicate glass.

PHOTOLITHOGRAPHY

• See lithography.

PHOTOMASK

• A fused silica (quartz) plate, typically 152mm square, covered with a pattern of opaque, transparent and phase-shifting areas which will be projected onto wafers in the lithography process to define the layout of one layer of an integrated circuit.

PHOTORESIST

• A light-sensitive organic polymer that is exposed by the lithography process, then developed to produce a pattern which identifies the areas of the underlying film to be etched.

PITCH

• The distance between the centers of adjacent features, for example interconnect lines or contact holes.

PITCH-HALVING

• Any patterning technique that creates paired, features from a single lithography image with a pitch half that of the original image, thus creating smaller patterns than the lithography process alone is capable of. Sometimes misleadingly referred to as pitch-doubling.

PIXEL DENSITY

• In FPD technology, a measurement of resolution that describes the distance between individual pixels on the display. Usually expressed in pixels per inch, or ppi.

PLANARIZATION

• The process by which an uneven wafer surface is made relatively flat using a low-selectivity etch or through CMP.

PLASMA

• A fourth state of matter - not a solid, liquid or gas. In a plasma, the electrons are pulled free from the atoms and can move independently. The individual atoms are charged, even though the total number of positive and negative charges is equal, maintaining an overall electrical neutrality.

PMD (PRE-METAL DIELECTRIC)

• Insulating layers deposited over the completed transistors at the end of FEOL processing upon which the first metal interconnect layer is formed.

PMOS or PFET

• P-channel MOS transistor where the active carriers are holes flowing between p-type source and drain regions in an electrostatically formed p-channel in an n-type silicon substrate.

PNA (POST NITRIDATION ANNEAL)

• An RTP step used to reduce leakage current without drive current loss after gate oxide nitridation in the creation of the gate stack.

POLYCIDE

• A film stack commonly used for the gate electrode in DRAM fabrication, consisting of tungsten silicide on polysilicon.

POLYSILICON

• Polycrystalline silicon (or semicrystalline silicon, polysilicon, poly-Si, or simply "poly") is a material consisting of multiple small silicon crystals. Extensively used as conductor/gate materials in a highly doped state. Poly films are typically deposited by pyrolyzing silane using an LPCVD process.

PPI (PIXELS-PER-INCH)

• A parameter use to measure the linear pixel density of an FPD.

PRE-AMORPHIZATION

• A technique used in ion implantation used to reduce channeling by intentionally amorphizing a region before dopant implantation, thus enabling a more uniform dopant profile to be attained. Within an amorphized region there is no channeling, by definition. A pre-amorphization implant is typically done with an inert element such as Argon.

PRE-SILICIDE IMPLANT

• A damage engineering technique used to lower transistor contact resistance.
• The contact region is co-implanted with a species such as carbon using cryo-implantation to enhancing the subsequent deposition of the nickel silicide (NiSi) contact metal.

PREDEPOSITION

• The last implant done before deposition of metal.

PROCESS

• An operation or group of sequential operations performed in the manufacture of an integrated circuit or other device.

PROCESS CHAMBER

• An enclosed area in which a single process is performed in the manufacture of an integrated circuit or other device.

PROCESS INTEGRATION

• Optimizing each process step to work correctly with the prior and subsequent steps in a sequential process flow.

PROFILOMETER

• Measuring instrument used to measure a surface profile in order to quantify its roughness and critical dimensions such as steps, curvature, flatness, texture and height.

PROJECTED CAPACITANCE TOUCH (PCT)

• A type of touch panel that consists of a grid of electrodes that can detect distortions of an electrostatic field caused by the presence of a conductive object such as a finger or conductive stylus.
• PCT panels are commonly used for applications that required the precise tracking of multiple contact points simultaneously, such as smartphones and tablet PCs.

PV (PHOTOVOLTAIC)

• A process where light is converted to electricity. Solar PV is the generation of electricity from solar radiation.

PVB (POLYVINYL BUTYRAL)

• A resin used in the manufacture of thin film PV modules. The PV circuit, formed on a sheet of glass, is covered in a sheet of PVB and then the back glass. This assembly is then laminated to encapsulate the circuit, protecting it from the environment.

PVD (PHYSICAL VAPOR DEPOSITION)

• A process technology in which atoms of conducting material (aluminum, titanium nitride, etc.) are sputtered from a target of pure material, then deposited on the substrate to create the conducting circuitry within an integrated circuit or FPD.

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QUADRUPLE PATTERNING

• A class of patterning techniques designed to quadruple the density of circuit features that can be produced on the wafer at the resolution limit of a particular lithography stepper.

QUADRUPOLE LENS

• A magnetic or electrostatic field generated by four poles of alternating signs arranged in a circle; used to focus a beam of charged particles.

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R2R (RUN-TO-RUN CONTROL)

• An APC technique that allows modification of a processing parameters between machine "runs" to minimize variability.

RADICAL

• An atom or group of atoms that has at least one unpaired electron and is therefore unstable and highly reactive.

RAMAN SPECTROSCOPY

• A spectroscopic method of chemical analysis that relies on the inelastic (Raman) scattering of monochromatic light. Enables real-time reaction monitoring and characterization of compounds in a non-contact manner.

RAPID THERMAL PROCESSING (RTP)

• An anneal process in which a wafer is heated to a specified temperature for a short period of time.
• RTP is repeatedly used during semiconductor device manufacturing for such purposes as activating implanted dopants or changing the state (or phase) of materials to enhance desired attributes (e.g., conductivity). Annealing can be performed using three technologies – soak, spike, and millisecond. The choice of technology depends on several factors, including the tolerance of the device to withstand a certain temperature/time exposure at a particular point in the manufacturing sequence. Broadly speaking, devices can bear longer periods of exposure (30-90 seconds), also known as soak annealing, at high temperatures early in the manufacturing cycle. As the cycle progresses, temperatures must either be lowered or exposures significantly shortened if high temperatures are required. Spike annealing falls in the latter category and is used for source-drain implant activation and diffusion as well as high-k/metal gate fabrication.

RC TIME CONSTANT

• How an RC circuit behaves over time when responding to a change in voltage, and is equal to the product of the circuit resistance and circuit capacitance. 

RE-ENTRANT PROFILE

• One that is angled inward. Refers to features whose sidewalls are concave.

RECIPE

• The memorized parameters for a particular process step, such as gas flows temperature and pressure. In general, the same recipe is used for all wafers in a lot.

REDISTRIBUTION LAYER (RDL)

• An extra metal layer on a chip that makes the input/output pads of an integrated circuit available in other locations, making chip-to-chip bonding easier.

RENEWABLE ENERGY STANDARD (RES)

• See renewable portfolio standard.

RENEWABLE PORTFOLIO STANDARD (RPS)

• A regulation that requires the increased production of energy from renewable energy sources, such as wind, solar, biomass, and geothermal. Another common name for the same concept is renewable electricity standard (RES).

RESISTANCE

• A measure of the degree to which conducting material opposes an electric current passing through it.

RESOLVING APERTURE

• In ion implantation, a small aperture, usually found directly after the analyzer, which resolves the beam to only one type of molecule or atom with a specific charge.

RETICLE

• A flat, transparent plate, used in a stepper that contains the image of wafer patterns to be reproduced on a wafer. Often used interchangeably with photomask.

RETINA DISPLAY

• A trademark of the Apple Corporation used to describe any display where the pixel density is sufficiently high that the human eye cannot distinguish individual pixels.
• Note that this term does not directly correlate with pixel density, because it includes the viewing distance. For a mobile phone screen to qualify as a retina display it should have a pixel density in excess of 300ppi, but a television need only be approximately 50ppi.

RF (RADIO FREQUENCY)

• In semiconductor fabrication, the oscillation rate of an electromagnetic or electrostatic field in the range of 2MHz-200MHz or 1-3GHz. In some types of wafer processing chambers, plasma is initiated by applying strong RF fields to the ESC, roof inductive structures, or roof capacitive structures; the oscillating electric field ionizes the gas molecules by stripping them of electrons to create the plasma.

RF PVD (RADIO FREQUENCY PVD)

• A type of PVD process that uses an inductively-coupled plasma to allow lower ion energies compared to conventional PVD reactors, and thus a more gentle deposition mechanism that can create very thin, sub-nanometer films and virtually eliminate damage to the underlying circuit features.

RIBBON BEAM

• in ion implantation, an electron beam that has been confined into a rectangular cross section allowing the entire surface of a wafer to be covered by steering the beam along a single axis. As opposed to a spot beam which must be scanned back and forth to cover the wafer.

RIE (REACTIVE ION ETCH)

• An etching technology that uses chemically reactive plasma to remove material deposited on wafers. High-energy ions from the plasma react with material on the wafer surface.

ROUGHING PUMP

• A mechanical pump used for the initial evacuation of a vacuum system. The process is called "roughing."

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SACVD (SUB-ATMOSPHERIC CHEMICAL VAPOR DEPOSITION)

• A term coined by Applied Materials to describe CVD processes performed slightly below atmospheric pressure using TEOS/ozone chemistry.

SADP (SELF-ALIGNED DOUBLE PATTERNING)

• A double patterning technique employing sacrificial sidewall spacer films to achieve pitch-halving.

SALICIDE

• A contraction of self-aligned silicide. Salicide processing technology seeks to exploit the principle that a refractory metal deposited on a patterned silicon substrate will selectively react with exposed silicon under specific processing conditions, and will not react with adjacent materials, such as silicon oxide material. Thus, no patterning step is required.

SAQP (SELF-ALIGNED QUADRUPLE PATTERNING)

• A patterning technique employing sacrificial sidewall spacer films to achieve four times higher resolution than the normal limits of a particular lithography stepper.

SCAN

• In ion implantation, the movement of the ion beam relative to the wafer in order to cover the entire wafer surface.

SCANNER

• A component of an ion implanter that either moves the ion beam across the wafer, or moves the wafer through the ion beam. This may be accomplished with a magnetic field, an electrostatic field or with mechanical motion.

SCANNING ELECTRON MICROSCOPE (SEM)

• A microscope that uses an electron beam rather than light to illuminate the sample. The beam is scanned back and forth across the sample surface.

SCREEN

• In crystalline silicon solar PV manufacturing, a sheet of woven material supporting a stencil with open areas through which silver paste or other materials is forced by a roller or squeegee to form a pattern on a wafer. It is analogous to the photomask in semiconductor manufacturing.

SCREEN OXIDE

• In ion implantation, a thin, sacrificial layer of SiO₂ which stops stray ions entrained in the ion beam and which will be subsequently removed. In addition, the screen oxide slightly scatters the main ion beam thus prevents channeling.

SECONDARY VACUUM PUMP

• Any vacuum pump which cannot exhaust directly to atmosphere, i.e. that must work in tandem with a roughing pump. Commonly used secondary pumps in semiconductors are cryopumps and turbopumps.

SECS/GEM (SEMI EQUIPMENT COMMUNICATION STANDARD/GENERIC EQUIPMENT MODEL)

• A software protocol used to standardize communication between semiconductor manufacturing equipment and the host control system. It was designed to simplify factory automation by establishing a common set of instructions that would be understood by all the equipment in a fab.

SEED LAYER

• A nucleation layer where the nucleation material is the same as the subsequently deposited film.

SELECTIVE

• Occurring only where desired without affecting neighboring materials, as in selective deposition or selective removal.

SELECTIVE EMITTER

• A technique used to increase the conversion efficiency of crystalline silicon PV solar cells. Selective emitters are heavily-doped regions placed precisely underneath the front metal contact lines in order to reduce electrical contact resistance and allow electricity to flow more freely. The doped regions are typically fabricated by depositing dopant paste on the surface of the wafer and then printing the contact lines on top.

SELECTIVITY

• The ratio of etch rates observed in two materials during etch processing. Typically used to refer to the relative etch rates of a material intended for removal and the mask, and an important metric of etch pattern fidelity.

SEMICONDUCTOR

• A material whose electrical conductivity is intermediate between that of metals (conductors) and insulators (non-conductors) and can be modified physically or chemically to increase or decrease its conductivity by the addition of dopants.

SILANE (SiH4)

• A gas that readily decomposes into silicon and hydrogen, silane is often used to deposit silicon- containing compounds. It also reacts with ammonia to form silicon nitride, or with oxygen to form silicon dioxide.

SILICIDATION

• An anneal (sintering) process resulting in the formation of metal-silicon alloy (silicide) to act as a contact. For example, Ti deposited on Si forms TiSi₂ as a result of silicidation.

SILICIDE

• A compound of silicon with a more electropositive element. Nickel, tantalum, titanium and cobalt silicide films are used to create ohmic (low-resistivity) contacts for transistor connections. Molybdenum silicide is commonly used as a light-absorbing layer in photomasks. Tungsten silicide (polycide) is used for DRAM gate electrodes.

SILICON

• Second most abundant element on Earth characterized with the symbol Si. Silicon is used as the main material for fabricating integrated circuits.

SILICON CARBIDE

• Semiconductor materials made of silicon and carbon characterized with the symbol SiC. This material moves electrical energy more efficiently, which makes it ideal for power electronics.

SILICON DIOXIDE (SiO₂)

• The most common dielectric material used in semiconductor manufacturing, due to its versatility and stability. Also known simply as "oxide", it can be grown direction on silicon wafers via thermal oxidation or deposited via PECVD or HDP-CVD processes.

SILICON NITRIDE (Si₃N₄)

• A silicon/nitrogen film dielectric deposited using plasma-enhanced or LPCVD. Sometimes loosely referred to as SiN.

SINGLE JUNCTION

• A PV cell constructed with a single p-n junction. This includes amorphous silicon thin film and most crystalline silicon cell types.

SIP (SELF-IONIZED PLASMA)

• A high-power magnetron source for PVD processes which imparts sufficient energy to the plasma such that the sputtered metal atoms are ionized. The metal ions can then be accelerated towards the wafer using an electric field, creating a more directional deposition pattern and thus higher step coverage in small geometry structures.

SLURRY

• In semiconductors, a suspension of abrasive solids in a liquid used for CMP processes. In PV, used as the abrasive medium in a wire saw for wafering.

SMO (SOURCE-MASK OPTIMIZATION)

• Source-mask optimization (SMO) is a resolution enhancement technique used in lithography to compensate for image errors due to aberrations, diffraction or process effects.

SOI (SILICON-ON-INSULATOR)

• The use of a layered silicon-insulator-silicon substrate in semiconductor manufacturing. SOI substrates provide reduced parasitic capacitance between adjacent devices in an integrated circuit as compared to devices built into bulk wafers, enabling reduced power consumption and thus higher device performance.

SOLAR CELL

• A device that converts the energy of sunlight directly into electricity by the photovoltaic effect. Multiple cells are wired together to form modules.

SOLAR FARM

• A utility-scale photovoltaic power station.

SOURCE

• The input terminal of an FET.
• In ion implantation, the source of the desired dopant species that are processed into a plasma from which the ion beam is extracted.
• In plasma processes such as etch, the energy source that is used to create and sustain the plasma in the reaction chamber.

SOURCE-DRAIN EXTENSION

• A lightly-doped region extending from the source or drain into the transistor channel designed to spread out the electrical field during operation of a transistor device. Without the extension, the electric fields in very small transistors may be sufficient to damage the gate dielectric and cause device failure.
• The ion implantation process used to create the source-drain extension is an example of damage engineering.

SPC (STATISTICAL PROCESS CONTROL)

• A method for improving quality control in manufacturing by applying statistical techniques to the monitoring and control of a process.

SPILLOVER CUP

• A stationary cooled metal plate, located on top of an implant disk, that captures the ion beam during overscan.

SPLIT LOT

• When different recipes are used within a lot for experimental purposes to improve the performance of a particular process step, the lot is referred to as a split lot.

SPUTTERING

• A method of depositing a film where atoms are ejected from a solid target material due to bombardment of the target by energetic particles.

SQUARING

• In PV wafer manufacturing, the process of cutting silicon ingots into rectangular blocks using a specialized wire saw. The squared blocks, or bricks, are then sliced into individual wafers in the wafering process.

SRAM (STATIC RANDOM ACCESS MEMORY)

• A type of computer memory where each bit is stored in a network of usually 6 or 8 transistors which has two stable states.
• SRAM cells are complex and consume more area on a chip than DRAM cells, but are much faster and more power-efficient.
• Microprocessors and other logic chips are often fabricated with SRAM cells on die for use as cache memory, used to store the most frequently accessed instructions and data.

SRU (SLURRY RECOVERY UNIT)

• A machine used in wafering and CMP that processes used slurry in order to recover material such as abrasives and cooling for subsequent recycling.

STEP COVERAGE

• The ratio of thickness of film on the sides of a feature to the thickness of the film at the bottom (e.g., in a via) or over the top of a feature (e.g., fins of a FinFET) respectively.

STEPPER

• Equipment used to transfer a reticle (photomask) pattern onto a wafer. The same pattern is transferred onto each die on the wafer.

STI (SHALLOW TRENCH ISOLATION)

• A technique to isolate each transistor or memory cell from its neighbors in order to prevent current leakage. The technique employs a pattern of trenches etched in the silicon, filled with an insulating material such as silicon dioxide.

STOCHASTIC DEFECT

• Random defects such as contacts, line edge roughness or pattern collapse that are more prevalent in EUV lithography.

STRAIN ENGINEERING

• Processes used in semiconductor manufacturing that introduce stress into transistors and memory cells by distorting the crystal lattice. In logic, this enables electricity to move more easily through the transistor, increasing transistor performance. In memory, strain can also reduce leakage current, allowing higher cell densities.

STRUCTURED WIRE

• A kind of cutting wire used in wire saws that is formed, or crimped, into a sawtooth or similar profile in order to increase cutting speed.

SUBSTRATE

• The material upon which thin films are manipulated. Silicon is most commonly used for semiconductors and c-Si PV cells. Glass is commonly used for LCD and thin film PV applications.

SUPERLATTICE

• A periodic structure of thin layers of two semiconductor materials.

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TANDEM JUNCTION

• A solar PV cell type that uses multiple light converting materials to increase conversion efficiency. Tandem junction thin film silicon cells, for example, use amorphous silicon and microcrystalline layers.

TARGET

• In PVD, the target is the source of the material to be deposited. Atoms are ejected from the target as a result of the bombardment of energetic particles.

TCO (TRANSPARENT CONDUCTIVE OXIDE)

• Doped metal oxide films used in optoelectronic devices such as flat panel displays, touch panels and photovoltaics. In LCDs, TCO layers form the electrodes that generate the electric field to polarize the liquid crystal. In touch panels, TCO layers are used for the sensing electrodes. In PV, the TCO forms the top electrode of the cell.

TEM (TRANSMISSION ELECTRON MICROSCOPE)

• A transmission electron microscope that transmits a beam of electrons through an ultra-thin specimen. It operates on the same basic principle as the optical microscope but with much higher resolution.

TEOS

• A liquid source for oxide deposition, Tetraethyl orthosilicate is the chemical compound with the formula Si(OC₂H₅)₄.

TERMINAL EFFECT

• The terminal effect is a phenomenon in electrochemical deposition whereby the deposited film tends to be thicker at the edge of the wafer than the center. It stems from a voltage drop that occurs from where the negative terminal contacts the wafer edge towards the center, due to the resistance of the wafer. A primary component of this resistance is the seed layer which is deposited on the wafer by PVD before the plating process. The seed layer becomes thinner at each technology node, which increases the resistivity of the wafer and exacerbates the terminal effect. The effect can be compensated for by using an advanced current density control system that can modulate the applied voltage across the wafer, resulting in uniform deposition across the wafer.

TFT-LCD (THIN-FILM TRANSISTOR LIQUID CRYSTAL DISPLAY)

• A type of LCD display that uses a thin-film transistor located at each pixel to directly drive the polarization of the liquid crystal, and thus control whether that pixel is on and off.

THERMAL FIELD EMISSION (TFE)

• eBeam technology, where electrons are emitted from a source at high temperatures to image a sample.

THIN FILM

• A layer of material ranging from fractions of a nanometer to several micrometers thick.

THIN-FILM TRANSISTOR (TFT)

• A MOSFET manufactured with thin film technology, used primarily in the manufacturing of active matrix LCDs.

THRESHOLD VOLTAGE

• Turns current on and off between the source and drain terminals.

THROUGH-SILICON VIA (TSV)

• A type of interconnect used in wafer-level packaging. A TSV is a vertical electrical connection, or via, that passes completely through the substrate to pass electrical signals between stacked die.

THROUGHPUT

• The number of wafers a tool can process per hour.

TILT

• In ion implantation, the angle at which the ion beam strikes the wafer measured from perpendicular. See also orient angle.

TOOL

• A term used to refer to a piece of semiconductor processing equipment.

TOOL OF RECORD

• Tool used for a specific semiconductor manufacturing process.

TOPOGRAPHY

• In semiconductor, non-planarity generated by the fabrication of features on the wafer surface. This can have significant effects on the patterning of subsequent layers because the limited depth of field of the stepper optical system may cause parts of the pattern to be out of specification. Also used to describe non-uniformity induced by different material removal rates in CMP.

TOUCH PANEL

• A type of computer interface that detects the presence of a stylus or finger on a typically rectangular area. Often integrated with a display to produce a touch screen.

TOUCH SCREEN

• A type of display, such as an TFT-LCD or AMOLED that incorporates a touch panel to enable the user to interact directly with the displayed image rather than indirectly via a mouse or trackball.

TRACK

• A tool that integrates several steps needed to process photoresist (deposition, soft bake, exposure, developing, hard bake) in semiconductor manufacturing.

TRANSISTOR

• A semiconductor device used to switch and amplify electronic signals that serves as the basic element of an integrated circuit.

TRENCH

• A groove etched in a wafer to be used as part of a device structure.

TRENCH CAPACITOR

• A capacitor built into a trench on the substrate. This technique allows capacitance can be increased without increasing the area on the wafer needed to form the capacitor.

TURBOMOLECULAR PUMP (TURBO PUMP)

• A type of secondary vacuum pump used to create a high vacuum. High speed turbine blades, alternating with stationary blades, compress gas molecules to the bottom of the pump for removal by a roughing pump.

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UHV

• See Vacuum.

ULTRA HIGH DOSE IMPLANTER

• See conformal plasma doping.

ULTRA-HIGH DEFINITION (UHD)

• A digital video format with a resolution of 3840 x 2160 pixels.
• Also known as 2160p and 4K, UHD has four times as many pixels as conventional HD 1080p video.

ULTRA-SHALLOW JUNCTION (USJ)

• An area of semiconductor manufacturing that is focused on reducing the thickness of the junctions that form the source and drain regions of advanced transistors in order to improve performance while maintaining acceptable leakage current and breakdown voltage.

UNDERBUMP METALLIZATION (UBM)

• Deposition process in flip-chip packages that connects the die to the substrate with solder bumps.

UNDOPED SILICATE GLASS (USG)

• An insulating film often used for PMD and ILD applications typically deposited using SACVD or HDP-CVD.

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VACUUM

• A pressure below atmospheric ambient, often referred to by specific pressure ranges:
  • Rough vacuum, from atmosphere to 1 x 10-3 Torr
  • High vacuum, from to 1 x 10-3 Torr to 1 x 10-9 Torr
  • Ultra-high vacuum (UHV) – below 1 x 10-9 Torr

VAPORIZER

• In ion implantation, a device used to convert solid state ion source material into a gaseous state for ion beam production.

VIA

• A vertical pathway through a dielectric layer that makes an electrical connection between interconnect layers.

VLSI (VERY LARGE SCALE INTEGRATION)

• A chip with between 10,000 and 1,000,000 transistors on a single die. The term is often extended to describe chips with any number of transistors greater than 10,000. Other terms such as ultra-large scale integration (ULSI) were coined, but are no longer in widespread use.

VNAND (VERTICAL NAND)

• Also known as 3D NAND array.
• A class of flash memory architectures where multiple two-dimensional arrays of memory cells are layered vertically on a single substrate (as opposed to stacking using wafer-level packaging).
• VNAND is a method of increasing bit density without necessarily decreasing the size of each individual cell.

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WAFER

• The thin, circular or nearly square slices of mono- or multicrystalline silicon on which semiconductors and PV cells are built.

WAFER FABBRICATION EQUIPMENT

• Equipment or tools that allow manufacturers to build integrated circuits; often used in reference to the market of manufacturers that build these tools.

WAFER-LEVEL PACKAGING (WLP)

• The technology of packaging an IC while still part of the wafer, rather than slicing the wafer into individual circuits (dice) and then packaging those.

WAFERING

• The process of dividing silicon ingots or bricks into wafers.

WAVEGUIDE

• In ion implantation, a rectangular vacuum duct located in the analyzer magnet region through which the beam passes.

WAVEGUIDE LINER

• A protective liner made of metal or graphite installed inside the waveguide. Unwanted ion species give up their energy on these liners.

WEB

• Another name for roll-to-roll coating technology, where thin films of material are deposited on rolls of flexible material.

WET CLEAN

• A process for removing unwanted material or contaminants from substrates using liquid chemistry between process steps.

WETTING

• Ability to spread out evenly over a solid surface instead of forming discrete droplets.

WIRE SAW

• A machine that uses a moving wire to perform three key steps in the manufacture of silicon wafers.
  1. Cropping - removing the tapered ends of monocrystalline silicon ingots.
  2. Squaring - turning the cylindrical cropped ingot into rectangular blocks, or bricks. In polycrystalline wafer manufacturing, this step is used to cut large cast ingots into bricks.
  3. Wafering - cutting the bricks into individual wafers.

WORD LINE

• Connection between gates of all transistors in a certain row of a memory array segment.

WORK FUNCTION

• The minimum amount of energy needed to remove an electron from the metal.

WP

• Watt peak, a solar industry unit for the power of a solar cell delivered under ideal irradiation conditions.

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YIELD

• The percentage of product (e.g., wafers or die) produced in a process that conforms to specifications.

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