Memory device performance requirements continue to grow more challenging as gate widths shrink at the 70nm technology node and below. Advanced gate and bitline structure requirements for low-resistivity films with low leakage current drive the transition from the conventional WSix gate material to PVD (Physical Vapor Deposition) WN/W films. For production worthiness, PVD WN/N films must also meet tight particle performance requirements at smaller gate critical dimensions.

Applied Materials offers the Endura CleanW PVD system which provides low defect WN/W films compatible with
≤70nm device fabrication. The CleanW chamber enables in-situ deposition of a very thin, low-resistivity WN/W film stack for gate and bitline applications. This technology has gained wide market acceptance for the production of 90nm DRAM and video CCD applications. The Endura CleanW is also used in 55nm Flash applications as the W gate electrode to achieve low gate Rs.

The optimized Endura CleanW deposition ensures film purity and process control, depositing, in-situ, a low-resistivity WN/W film stack that provides both a Si diffusion barrier and a W conductive layer in a single-chamber process. For equivalent conductivity, the WN/W film stack is 10x thinner than WSix and maintains high thermal stability (up to 1,000°C), in small device features. Together, these characteristics significantly improve manufacturing ease while enabling the transition to sub-70nm production.