After more than forty years of successfully improving logic device performance and packing density through transistor scaling, the traditional gate stack has reached a fundamental limit. Other techniques such as strain engineering offer innovative methods for increasing drive current, but continuation of Moore's law for power-efficient devices requires a completely new approach with a new set of materials and new integration schemes.
With the oxynitride dielectric becoming thinner, continued scaling of the gate dielectric electrical thickness is limited by an unacceptable increase in leakage. The implementation of a higher-k hafnium-based dielectric coupled with an atomically engineered oxynitride interface addresses gate leakage while maintaining high mobility devices. In conjunction with the new dielectric stack, metal gates are replacing polysilicon gate electrodes for material compatibility and performance. Devices made with high-k/metal gates can achieve >100x improvement in gate leakage, with significantly faster switching speeds.
High-k/metal gate implementation is not limited to Logic devices. Flash memories that traditionally employ floating gate devices are reaching scaling limits as well. Charge Trap Flash devices with nitride films have been proposed to replace the current poly-Si floating gates. With these changes, the SiO2 blocking oxide and poly control gate will be replaced by high-k gate dielectric and high work function metal, respectively.
There are multiple high-k/metal gate integration approaches being pursued. In addition to materials selection and unit process development, successful implementation of the new gate structures will depend on interface engineering, especially at the critical high-k interfaces. Applied Materials is poised to facilitate this major materials transition with its suite of deposition, etch, inspection/metrology and integration technologies available on proven manufacturing platforms.
Integrated High-k Dielectric Stack
Applied Materials delivers a high-mobility, low-leakage high-k dielectric solution comprised of a precision engineered high-k ALD film on a proven SiON interface layer. Through the unique integration of these two critical deposition processes on a single Centura platform, the dielectric-to-dielectric interface can be atomically engineered for optimum performance.
Integrated Metal Gate Stack
The industry leader in metal deposition technology, Applied Materials offers a broad portfolio of ALD and PVD technologies to address different metal gate schemes. With excellent step coverage, void-free gap fill, and process repeatability, metal deposition process technologies are integrated on the Endura 2 platform which offers benchmark reliability and productivity.
Integrated High-k/Metal Gate Etch
The industry's first high-temperature high-k etcher, the Applied Centura Carina Etch is a breakthrough in enabling the scaling of memory and logic devices beyond 45nm. Its high-temperature processing expands the process window for clean and complete high-k etching, eliminating the tradeoffs between vertical profiles and silicon recess that plague conventional-temperature processes.
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Conventional-Temperature
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High-Temperature
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Process Control For High-k/Metal Gate
Successful high-k/metal gate integration requires defect-free interfaces between each layer of the gate stack. Early detection and characterization of random and systematic defects enables acceleration of production ramp. UVision SP captures small pattern defects and sub-30nm residue before metal gate deposition, and SEMVision G3 STAR shortens time to defect resolution with unmatched SEM analysis image quality and productivity.
High resolution defect review
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Automatic EDX material analysis of defect
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News Features, Articles, and Related Events:
Applied HKMG ready when you are, Ed Korczynski, Wafer News, October 27, 2006†
Has the Time Arrived for Manufacturing High-k/Metal Gates?A symposium co-sponsored by IEEE SCV-EDS and Applied Materials, October 26, 2006
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